The present invention relates generally to modulation control for high power converters and more particularly to determining gate timings for power electronic switches in three phase power converters used in motor drive systems.
Baker et al., U.S. Pat. No. 4,270,163, proposed a three level inverter power circuit in a neutral point clamped (NPC) bridge inverter but did not provide a mechanism for neutral capacitor balance or a viable modulation technique for a vector controlled drive, both of which are necessary for using the power circuits in motor drive systems.
Various suggestions have been made to address the issues of how to use these proposed power circuits in motor drive systems. For example, Kratz, U.S. Pat. No. 4,855,893, describes a method of providing neutral voltage balance in which a twelve pulse rectifier source converter supplies independent stiff grid support of each half of the DC capacitor bank and in which switching safety of power devices is improved with a snubber design. This embodiment eliminates active control for capacitor voltage balancing and simplifies the controller requirements, but unfortunately cannot achieve the five percent total demand distortion (TDD) on the grid connect required by the IEEE-519 standard set by the institute of Electrical and Electronics Engineers (IEEE).
Early modulators were defined as sine-triangle hardware schemes or with off-line optimized switching patterns. More modern NPC modulator approaches based on space vector synthesis techniques have been developed using algorithms focusing on gate turn off (GTO) converters where large minimum gating time constraints (greater than 100 microseconds) are a dominant consideration. Active neutral voltage control was first described using sine-triangle modulation schemes with zero-sequence voltage insertion for voltage balance control. The zero sequence reference voltage was developed from capacitor voltage unbalance and power flow direction (motoring or regeneration). The space vector modulator synthesis algorithms were also modified to exploit redundant vector states in order to control the neutral voltage balance. Several space vector methods have included sub-dividing the vector space to avoid minimal pulse timing constraints of GTO switching elements by simultaneously controlling capacitor neutral voltage while minimizing switching frequency.
The power flow based neutral voltage balance control systems of the above techniques can have problems maintaining neutral control in high dynamic conditions.